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Eighteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

FPGA 2010

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Conflicts of Interest:

Please identify all potential committee members and reviewers who should not review this submission, due to having a conflict of interest with you or any of your co-authors. It is crucial that you fill in this section as carefully as possible, and that you do so in consultation with all of your co-authors. For more information on how to determine your conflicts of interest, please see the author guidelines posted at the website for FPGA.

Reviewer checklist: Please carefully examine the list of names below, and check-off any of the people who should not review this submission, due to a conflict of interest with one of the authors. (This also includes the names of any co-authors, if they appear below.)

 Jason Anderson     Vaughn Betz     Chen Chang     Deming Chen   
 Peter Cheung     Derek Chiou     Paul Chow     Katherine Compton   
 Jason Cong     Carl Ebeling     Jonathan Greene     Scott Hauck   
 Lei He     Brad Hutchings     Ryan Kastner     Martin Langhammer   
 Miriam Leeser     Guy Lemieux     Philip Leong     David Lewis   
 John Lockwood     Wayne Luk     Patrick Lysaght     Stephen Neuendorffer   
 Jonathan Rose     lesley Shannon     Satnam Singh     Juergen Teich   
 Russ Tessier     Steve Trimberger     John Wawrzynek     Steve Wilton   

Additional conflicts: The committee may call on external reviewers to help evaluate your submission. These reviewer names may not appear in the list above. Therefore, we also request that you identify any other conflicts of interest you can think of. Specifically, you should list anybody you know of who works in an area related to FPGA, and who has a conflict of interest with either you or one of your co-authors. (You do not need to include your own author names in this list.)

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logic element architecture
routing fabric architecture
architecture methodology
circuit design
leakage power
dynamic power
asynchronous design
I/O buffer or transceiver
power grid
process technology
nano-technology
yield analysis or optimization
SER/TMR/reliability
test/verification
timing/power modeling
place&route algorithm
synthesis algorithm
power-optimization algorithm
incremental algorithm
timing modeling or analysis
methodology
arithmetic application
DSP application
networking application
cryptography algorithm or application
automotive application
audio/video application
other application
embedded processor
reconfigurable computing
adaptive computing
application-specific computing
emulation
simulation acceleration
 
 

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